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| 1/3 january 2002 AN1427 application note interfacing the psd813f5 with the adsp-21061 sharc dsp contents (see next page)
i contents 1.0 introduction 1 2.0 purpose .... 1 3.0 psd813f1 architecture ..... 2 4.0 development systems .... 3 5.0 programming the psd813f in-circuit using the jtag isp interface .... 3 6.0 interfacing the psd813f5 with the adsp-21061 ... 5 6.1 psd813f5 bus interface..... 5 6.2 adsp-21061 bus interface timing calculation. 6 6.3 adsp-21061 memory map 8 6.4 interfacing to the adsp-21061 external memory map..... 9 6.5 define the adsp-21061 interface in psdsoft express define psd and mcu... 9 6.6 define the psd813f5 dpld decoding functions in psdsoft express edit/add logic statements.... 13 6.7 accessing the psd813f5 internal registers. 14 6.7.1 reading the contents of the internal registers. 14 6.7.2 writing to the internal registers... 14 7.0 in application re-programming using the adsp-21061 serial port . 14 8.0 adsp-21061 boot loader ... 16 9.0 summary .. 17 10.0 appendix .. 17 1 1.0 introduction the digital signal processing marketplace is typically divided into two specific areas: function and algorithm specific ics .are non-programmable dsps integrated with other peripherals. they consist of modem chips, dvds, mpeg and video decoders, etc . general purpose programmable dsps .are flexible dsps that are used in a broad spectrum of products. they typically use a microcontroller for control, as well as additional i/o and programmable logic. most general purpose dsps have internal 8-bit boot load routines embedded in rom which take advantage of slower, less expensive external flash and eproms to store non-volatile program code to upload into fast internal sram at reset. 2.0 purpose although the flash psd8xx family has become an ideal peripheral for 8-bit microcontrollers, many companies using the psd in dsp-based products have shown that it makes an excellent peripheral for dsps. the psd8xx provides programmable logic and the required bus interfacing to implement a clean two-chip solution. the psd jtag port allows in-system programming (isp) of a completely blank psd8xx device soldered to the board with no involvement of the dsp, which is ideal for first time programming during manufacturing. the psd8xx also offers in application re-programming (iap), in which the dsp participates by executing uart download code from the small flash memory in the psd while writing new code into the large flash memory in the psd. this unique concurrent operation of psd memories offers many iap options. after iap is complete, the dsp can copy the contents of the psd main flash into the fast dsp sram for full speed operation. this application note addresses the ease of interfacing the psd8xxf with the adsp-21061 dsp. familiarity with the psd8xxf is assumed. please reference psd813f data sheet for a detailed description of the device. the 21061 dsp is optimized for high performance signal computing for speech, sound, graphics and imaging applications. the psd8xxf family of zero power parts meets these criteria and enables the core dsp design to be done with two chips. 2 3.0 psd813f1 architecture the psd8xx family is complemented by a lower-cost psd9xx family. figure 1 is a block diagram of the psd8xx and psd9xxf. table 1 shows a comparison of the functional differences in the memory and cpld options. on-chip features supply the key elements to implement a two-chip dsp system. some devices have 32k bytes of byte-erasable eeprom that may be used in place of external sram in some designs. flash psd features include: 1. programmable bus interface to dsps that are capable of external 8-bit boot code and/or program code. 2. 128-256 kbytes of main flash memory divided into eight individually selectable segments, each with optional sector protection. 3. separate 32 kbytes eeprom or secondary flash memory divided into four individually selectable segments, each with optional sector protection. 4. concurrent memory operation of main flash and secondary memory (eeprom or flash) allows execution from one memory while reprogramming the other. 5. 2 kbytes or 8 kbytes of sram. 6. two flash-based plds with 16 output micro cells and 24 input micro cells. 7. 27 individually configurable i/o port pins. each may be defined as dsp i/os, pld i/os, latched dsp address outputs or special function i/os. 8. 8-bit page register to expand the address space by a factor of 256. 9. jtag-isp serial port for true in-system programming (isp) of blank devices and reprogramming of devices in the factory or field. table 1. psd8xxf and psd9xx product matrix device flash main memory 8 sectors (kbit) secondary memory for boot and/or data 4 sectors (kbit) sram (kbit) pld psd813f1 1024 256 eeprom 16 sequential psd813f2 1024 256 flash 16 sequential psd813f3 1024 none 16 sequential psd813f4 1024 256 flash none sequential psd813f5 1024 none none sequential psd833f2 1024 256 flash 64 sequential psd834f2 2048 256 flash 64 sequential psd913f2 1024 256 flash 16 combinatorial only psd934f2 2048 256 flash 64 combinatorial only 3 an adsp-21061 dsp is used in this application that has an on-chip boot loader feature and does not require an external boot block. well take advantage of this and select the low-cost psd813f5 that has main flash only (no secondary boot memory). 4.0 development systems the psd family is supported by psdsoft express, a software development tool that runs on windows 95 & 98 and nt. this tool has point and click features for dsp bus interface configuration, and uses an hdl (psdabel) to define general programmable logic within the pld. dsp firmware is imported and merged to create a single object file to program into the psd. psdsoft supports two device programmers directly (st psdpro, st flashlink). the generated object file is also compatible with third-party programmers. see web site for list ( www. st. com /psm ). st offers two low-cost device programmers: psdpro .plugs into a pc/laptop parallel port and replaces the st magicpro iii. flashlink .is a low cost cable that plugs into a pc/laptop parallel port to support jtag-isp programming. flashlink is controlled by psdsoft express and supports device chaining of multiple psds and devices from other manufacturers. 5.0 programming the psd813f in-circuit using the jtag isp interface the ability to initially program a new system board with a blank flash memory soldered directly to it has solved many manufacturing logistics problems C no sockets or individual labels are required; inventory of non-volatile program memory chips is reduced to one package; the pld is programmed at the same time as the memory chip. one system board can be built and inventoried. any options can be programmed into the flash memory at board level testing. port c i/o lines are used to interface to the standard jtag signals C tms, tck, tdi and tdo. tstat and terr are optional jtag-isp extensions that can be monitored to decrease the programming time of the psd813f. the psd configuration, pld logic, flash memory and optional flash boot/eeprom can be programmed simultaneously through this interface. port c also gives the option to multiplex its jtag pins with the psd813f general i/o lines. this option, if used, frees up the jtag pins for i/o functions after jtag programming is completed. this option is enabled by the following three lines of code in psdabel, and its hardware implementation is illustrated in application note 054 jtag information C psd813f: jen pin 11; port c pin pc7 is used as external jtag multiplex enable jtagsel node; selects jtag port active using internal product term jtagsel = !jen; switches port c between jtag and i/o 4 figure 1. C psd8xx/psd9xx block diagrams mcu addr/data mcu control page reg decode pld gpld 19 combinatorial logicoutputs 128k byte main flash 8 segments 32k byte secondary flash 4 segments 2k byte sram i/o port a i/o port b i/o port c i/o port d pow er mngt device security jtag-isp controller mcu addr/data/cntl bus pld bus i/o bus psd913f2 mcu addr/data mcu control page reg decode pld cpld 16 macro cells 3 combinatorial 128k byte main flash 8 segments eeprom 2k byte sram i/o port a i/o port b i/o port c i/o port d pow er mngt device security jtag-isp controller mcu addr/data/cntl bus pld bus i/o bus psd813f1 5 6.0 interfacing the psd813f5 with the adsp-21061 figure 2 is a block diagram that shows the bus interface implementation of a two-chip system using the psd813f5 and the adsp-21061. all glue logic, flash memory, bus interface logic, i/o, chip selects and plds are contained in one chip. figure 2. C block diagram C bus interface for minimized dsp system port a port b port c port d jtag & i/o port a0 - a23 /mstrb r/ w r/ w /ds /ds /iostrb adsp-21061 d16-d23 d16-d23 psd813f5 port a port b port c port d jtag & i/o port a0-a15 a16-a22 control lines data[23..16] addr[23..0] control ad[15..0] cntl[2..0] i/o 6 6.1. psd813f5 bus interface the psd813f5 has a user-friendly programmable bus interface that is quickly configured to interface directly to most general purpose dsps with no glue logic. table 2 lists the bus interface signals from the adsp-21061 used to access the flash memory, pld logic and i/o inside the psd813f5. table 2. C adsp-21061 bus interface pin functions adsp-21061 pin functions psd813f5 pin functions pin description addr31 C addr24 addr23 C addr16 addr15 C addr0 nc portb pb7 C pb0 ad15 C ad0 external address bus addresses external memory and i/o in bus master mode. data47 C data24 data22 C data16 data15 C data0 nc porta pa6 C pa0 nc 48 bi-directional external data bus lines. data22 C data16 are used to boot load from an external 8-bit flash memory. /bms cntl2 boot memory select. /bms is output in the bus master mode (eboot = 1, lboot = 0) to select the external flash boot memory. /rd cntl1 memory read strobe is output in bus master mode to read from external memory and i/o. /wr cntl0 memory write strobe is output in bus master mode to write to external memory and i/o. /ms3 - /ms1 ms0 nc portd pd0 memory select lines are active low chip selects for the four banks of external memory. 6.2 adsp-21061 bus interface timing calculation the adsp-21061 has an internal programmable wait register that generates 0 to 7 separate wait states for each of the four external memory banks. all flash program memory and i/o are located in bank 0. if the eeprom/boot flash and sram options are used, they also are located in bank 0. after the dsp is reset, all wait state registers are default to 6 wait states to allow access to slow memory. figure 3 compares the read/write timing differences between the adsp-21061-40 mhz and psd813f5-90ns. three wait states are required to access the program flash memory and i/o in the psd813f5 during normal program execution. all calculations are based on the /rd, /wr, /bms and /ms0 bus interface signals. 7 figure 3. adsp-21061 read / write memory timing addr 31 C 0 /ms , /bms t darl = 2 + w min t rw = 12.5 + w min /rd t rlqv = 38 max t hdrh = 2 t dad = 18 + w max t rhqx = 2 t avqv = 90 max data 48 C 0 t dawl = 3 min t avwl = 20 min t ww = 13 + w min /wr t wlwh = 20 min t wde = -1 t datwh = 1-6 t whdx = 5 min data 48 - 0 note: 1) the timing values are referenced as : adsp-21061 C 40 mhz psd813f5 C 90ns 2) adsp-21061 is the bus master accessing external memory. 8 6.3 adsp-21061 memory map the adsp-21061 contains 1 mbit configurable on-chip dual-port sram, organized as two banks of 0.5 mbit each. one bank is used primarily to store instructions and data, and the other bank is used to store data; other combinations are allowed. the memory is configured as 32k words data memory (32-bit), 16k words program memory (48-bit), or combinations of both. the memory map is shown in figure 4. four gigawords of external memory (32-bit address) are accessed via the external port, starting at address 0040 0000. the optional flash boot memory also starts at this address. four memory select lines (ms0 - ms3) are used as chip selects to access their corresponding external memory banks. figure 4. adsp-21061 memory map internal memory space external memory space 0000 0000 0040 0000 0002 0000 /ms 0 0004 0000 /ms 1 0008 0000 /ms 2 multi- / ms 3 processor memory space 0038 0000 003f 0000 ffff ffff normal word addressing: 32-bit data words 48-bit instruction words short word addressing: 16-bit data words iop registers normal word addressing short word addressing internal memory space broadcast write to all adsp-21061x bank 0 dram (optional) bank 1 bank 2 bank 3 nonbanked 9 6.4 interfacing to the adsp-21061 external memory bus the block diagram of figure 5 shows the bus interface between the adsp-21061 and the psd813f5. since the boot code in external flash memory begins at address 0040 0000, 23 of the 32 address lines are used by the psd813f5. also, only data lines data16-data22 are utilized to transfer 8-bit program/data to the dsp. paging is not required, due to the 32 available external address lines. figure 5. block diagram C adsp-21061 system block diagram port a port b port c port d jtag & i/o po rt a0 - a22 /mst rb r/ w r/ w /ds /ds /io strb adsp-21061 d16-d23 d16-d23 psd813f5 port a port b port c port d jtag & i/o po rt a0-a15 a16-a22 /w r /w r /rd /rd /b m s cntl2-/psen /m s0 i/o 6.5. define the adsp-21061 interface in psdsoft express define psd and mcu utility figure 6 is the mcu and psd selection screen imported from psdsoft express define psd and mcu utility. selecting the following appropriate signals in this screen quickly configures the bus configuration between the adsp-21061 and psd813f5. /mso is connected to the psd813f5 dpld through port d (pin pd0) and included in the internal chip select equations generated under the chip select equations tab in the design assistant screen. * type: other * data bus width: 8-bit * address / data mode: non-mux * control setting: /wr, /rd figure 6. define psd and mcu 10 figure 7 is the schematic diagram of the adsp-21061 / psd813f5 bus interface. the 128k bytes of psd813f5 flash memory reside in data space, because program code will not be executed from external flash memory; it will be downloaded to the internal dsp daram. this iap feature allows updated program code to be downloaded to the flash memory through the dsp serial port for future download to the daram for program execution. 11 figure 7. schematic diagram C adsp-21061 to psd813f5 bus interface vcc addr19 data22 data20 data18 data17 data21 addr22 addr20 addr21 addr18 addr16 data23 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 data19 addr17 jtag 1 2 3 4 u2 psd813f5 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 46 20 19 18 17 14 13 12 11 47 50 49 10 9 8 48 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 pco/tms pc1/tck vstby pc3/tstat pc4/terr pc5/tdi pc6/tdo pc7/bhe cntl0-r/w,wr cntl1-e,rd,ds cntl2-psen pd0-as-ale pd1-clkin pd2-csi reset adsp-21061 u1? 13 14 16 17 18 20 21 22 24 25 26 28 29 30 32 33 35 36 37 40 41 42 44 45 46 50 51 52 60 64 65 66 94 93 59 57 56 55 54 178 179 177 175 174 173 171 170 169 167 166 165 163 162 161 159 158 157 155 154 153 151 150 149 235 232 234 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 addr19 addr20 addr21 addr22 addr23 addr24 addr25 addr26 addr27 addr28 addr29 addr30 addr31 /wr /rd /bms /ms0 /ms1 /ms2 /ms3 data1 data0 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 data16 data17 data18 data19 data20 data21 data22 data23 eboot lboot /reset adsp-21061 13 14 16 17 18 20 21 22 24 25 26 28 29 30 32 33 35 36 37 40 41 42 44 45 46 50 51 52 60 64 65 66 94 93 59 57 56 55 54 178 179 177 175 174 173 171 170 169 167 166 165 163 162 161 159 158 157 155 154 153 151 150 149 235 232 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 addr19 addr20 addr21 addr22 addr23 addr24 addr25 addr26 addr27 addr28 addr29 addr30 addr31 /wr /rd /bms /ms0 /ms1 /ms2 /ms3 data1 data0 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 data16 data17 data18 data19 data20 data21 data22 data23 eboot lboot dsp interrupt /reset data16 (optional) rdy/bsy 12 6.6. define the psd813f5 dpld functions in psdsoft express edit/add logic statements figure 8 is the system memory map created for this application note defining the internal decoding functions for the adsp-21061 based system. no paging is required, due to its 4- gigaword external memory address range. all functions of the psd813f5 are mapped in bank 0 of the external memory space. for this example, the external memory bank size is set to one megaword by setting the msize bit field of the syscon register. the i/o and chip select addresses are defined in the psdsoft express design assistant screen under chip select equations and implemented in the internal psd813f5 decoding pld (dpld). see appendix for psdsoft express design assistant summary. figure 8. adsp-21061 system memory map external memory space 0040 0000 004e 0000 bank 0 004e 8000 /ms0 = 0 or /bms = 0 004e a000 004f ffff /ms1 = 0 /ms2 = 0 /ms3 = 0 psd813f5 flash memory 896 kbytes (768 kbytes reserved for future psd8xx/9xx) psd813f1 eeprom/boot flash 32 kbytes (optional) optional psd8xx/9xx sram 2-8 kbytes psd813f5 i/o space 88 kbytes bank 1 bank 2 bank 3 non-banked 13 6.7accessing the psd813f5 internal registers the bank of internal control registers in the psd813f5 (csiop + hxx) are 8-bits wide and are not accessible on a 16-bit word boundary; they must be addressed on 8-bit byte boundaries. the boot select override (bso) bit in the adsp-21061 syscon register provides this capability. also, the internal registers must be mapped in the memory area that is accessible by /bms 6.7.1 reading the contents of the internal registers the bso bit overrides the external memory selects and causes the /bms pin to go active low for an external port dma transfer. the bootstrap program should first set the bso bit in the syscon register and then set up one of the four external dma channels to access the external non-boot memory. while one of the external port dma channels is being used with the bso bit, the other three channels cannot be used. when bso = 1, /bms is not asserted by a dsp access to the boot code, but by a dma transfer. this allows the bootstrap program in the dsp core to access the psd813f5 internal registers instead of boot memory. 6.7.2 writing to the internal registers the bso bit in the syscon register allows the /bms signal to write to external 8-bit memory under software control. to write to the internal registers with /bms active, use dma channels 7, 8, or 9, but not channel 6, which is hardwired for a special 8-bit boot read mode. since bms memory space is 8-bits wide and no 8-bit packing mode is available for these write accesses, the dsp shifter must be used to place data on data lines data16-data23 for each write. 7.0. in application re-programming (iap) using the adsp-21061 serial port the psd813f5 (without secondary memory) was selected to reduce the system cost and take advantage of the dsp daram that can contain the program code for iap of psd flash memory through the dsp serial port. the synchronous serial port of the adsp-21061 is used for field updates to the program code that resides in one or more sectors of the psd813f5 flash memory; these sectors are located in bank 0 of external memory space. each chip select for each flash sector C fs0..fs7 C has three product terms that enable control of individual flash sector(s) to easily switch between /bms for downloading boot code during power-up and reset, and /ms0 to field upgrade program code as if it were data memory. the psdabel file in the appendix shows how the abel equations are written to swap all eight flash sectors between program and data control. page register pgr7 is used a swap bit to switch the flash memory chip select(s) control between /bms and /ms0. the adsp-21061 has 32-bit transmit and receive data buffers with selectable word lengths from 3 to 32 bits. an 8-bit programmable word length is right-justified in the receive and transmit buffers. when a boot program update is received by the serial port, the 8-bit data in the receive data buffer is shifted left to align with the external data bus bits data23-data16 and written 14 to the accumulator to store either in an asigned section of the dsp daram allocated as a buffer for the uploaded program code, or write to the flash memory on a byte-by-byte basis. the byte-by byte write sequence to the flash memory can be speeded up dramatically by configuring the rdy/busy polling bit to port c (pin pc3) and using it as an interrupt input to the dsp. once a byte write command is issued, the time required to program the byte can now be executed in background mode. the dsp can be performing other tasks until the rdy/busy pin signals that the byte has been successfully programmed and generates an interrupt. the rdy/busy bit is hardware configured as an output interrupt pin as shown in figure 10 with the configuration sequence as follows: 1. select pc3 from the psdsoft express pin definition screen. 2. select rdy/bsy output in other block. figure 9. psdsoft express C pin definition screen 15 adsp-21061 boot loader the adsp-21061 supports three modes of booting: eprom, host and link port. each bootmode packs boot code into 48-bit instructions and uses dma channel 6 to transfer the instructions to internal daram. table 4 lists the available boot mode options. eboot = 1 and lboot = 0 is selected for this application. table 4. adsp-21061 boot mode options eboot lboot bms boot mode 1 0 output boot memory is loaded from an 8-bit external flash/eprom 0 0 1 (input) boot memory is loaded from a 16-bit host processor 0 1 1 (input) link port accesses 4-bit boot memory through dma channel and ext.clock 0 0 0 (input) no booting. adsp-21061 executes code from external memory eprom/flash booting is selected when eboot input is strapped high, configuring /bms as an output to be used as the boot flash chip select. eprom/flash mode only loads 256 instructions during boot loading. the adsp-21061 must have access to the boot/flash memory after completion of the bootloading to download the entire application into daram. the primary configuration of the dsp dma channel 6 is used for flash and host booting. table 5 shows how the dma channel 6 parameter registers are initialized at reset for flash booting. table 5. dma channel 6 registers initialization values parameter register initialization value description ii6 0x0002 0000 starting address of internal memory space c6 0100 contents of count register to transfer 256 words to internal memory ei6 0x0040 0000 starting address of external memory space ec6 0600 external count register C transfers 256 words (6 bytes/word) 8.1. boot loader sequence after system reset (/reset = 1), the following sequence of events occur: 1. the adsp-21061 enters an idle state. the program counter (pc) is set to address 0x0002 0004. 2. the dma parameter registers for dma channel 6 are initialized as shown in table 5. 3. /bms becomes the boot flash memory chip select. 4. 8-bit master mode dma transfers from flash to internal sram memory begin, using external port data bus lines data23 - data16. 5. the external address lines addr31 C addr0 start at address 0x0040 0000 and increment after each access. 6. the /rd strobe asserts as in a normal memory access, with six wait states. 16 when the external count register (ec6) reaches zero, the following wake-up sequence occurs: 1. the dma transfer stops. 2. the external port dma channel 6 interrupt (epoi) is activated. 3. /bms is deactivated and normal external memory selects are enabled. 4. the adsp-21061 vectors to the epoi interrupt vector at 0x0002 0040. 5. the adsp-21061 booting mode is complete and instructions are executing normally. 8.0. summary as dsps continue to rapidly proliferate into markets such as communications, industrial, medical, signal conditioning, and hand held test equipment, the psd813f and dsp form an ideal 2-chip core with on-chip pld and 27 i/o lines that can be individually configured to perform any function required by the system design. using the psd813f as an 8-bit boot loader in both high speed and low speed systems is an ideal and rapid design alternative to a discrete solution. inexpensive slower memory and plds integrated in the psd813f now become both cost and performance effective. several features internal to the psd813f5 were used to expand the limitations of the adsp- 21061, and dsps in general: 1. flash memory allows iap update of the program code in the field through the serial port of the dsp while the dsp is running program code in the internal daram. 2. jtag-isp simplifies manufacturing. 3. expanded i/o was added to the system. 4. the internal flash pld allows design changes, in logic, i/o and memory mapping, to be made by software modifications instead of board level hardware changes. these changes have added to both the versatility and performance of the adsp-21061; future changes most likely will not require a hardware change to the 2-chip core. 9.0. appendix the appendix contains the psdsoft express design assistant summary showing how the psd813f5 is configured to implement the example of this application note. 17 *********************************************************************** psdsoft express version 6.02 summary of design assistant *********************************************************************** project : ad_21061 date : 09/26/2000 device : psd813f5 time : 17:27:05 mcu : 18 user defined nodes: =================== none defined page register settings: ======================= pgr0 is not used pgr1 is not used pgr2 is not used pgr3 is not used pgr4 is not used pgr5 is not used pgr6 is not used pgr7 is used for logic, signal name: swap equations: ========== csiop = ((address >= ^h4ea000) & (address <= ^h4ea0ff) & (!_bms)); fs0 = ((address >= ^h400000) & (address <= ^h403fff) & (!_bms & !swap)) # ((address >= ^h400000) & (address <= ^h403fff) & (!_mso & swap)); fs1 = ((address >= ^h404000) & (address <= ^h407fff) & (!_bms & !swap)) # ((address >= ^h404000) & (address <= ^h407fff) & (!_mso & swap)); fs2 = ((address >= ^h408000) & (address <= ^h40bfff) & (!_bms & !swap)) # ((address >= ^h408000) & (address <= ^h40bfff) & (!_mso & swap)); fs3 = ((address >= ^h40c000) & (address <= ^h40ffff) & (!_bms & !swap)) # ((address >= ^h40c000) & (address <= ^h40ffff) & (!_mso & swap)); fs4 = ((address >= ^h410000) & (address <= ^h413fff) & (!_bms & !swap)) # ((address >= ^h410000) & (address <= ^h413fff) & (!_mso & swap)); fs5 = ((address >= ^h414000) & (address <= ^h417fff) & (!_bms & !swap)) # ((address >= ^h414000) & (address <= ^h417fff) & (!_mso & swap)); fs6 = ((address >= ^h418000) & (address <= ^h41bfff) & (!_bms & !swap)) # ((address >= ^h418000) & (address <= ^h41bfff) & (!_mso & swap)); fs7 = ((address >= ^h41c000) & (address <= ^h41ffff) & (!_bms & !swap)) # ((address >= ^h41c000) & (address <= ^h41ffff) & (!_mso & swap)); AN1427 - application note 2/3 table 1. document revision history date rev. description of revision sep-2000 2.1 document written (an071) in the wsi format 03-jan-2002 2.2 front page, and back two pages, in st format, added to the pdf file 3/3 AN1427 - application note for current information on psd products, please consult our pages on the world wide web: www.st.com/psm if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. 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